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Computer Science · Q168

Digital Computer Electronics

Engineering and GATE · Computer Science · question 168

Q168

For an input pulse train of clock period T, the delay produced by an n stage shift register is

A.
(n-l)T
Answer
B.
nT
C.
(n+l)T
D.
2nT
E.
None of the above

Answer: Option A

Solution

Answer: Option A
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