The pipelining process is also called as . . . . . . . .
A. Superscalar operation
B. Assembly line operation
C. Von Neumann cycle
D. None of the mentioned
Select an option to see the answer and solution.
. . . . . . . . symbol is used to signify write back mode.
Select an option to see the answer and solution.
. . . . . . . . signal is sent by the initiator to indicate the duration of the transaction.
A. FRAME#
B. IRDY#
C. TMY#
D. SELD#
Select an option to see the answer and solution.
Since it uses the out of order mode of execution, the results are stored in . . . . . . . .
A. Buffers
B. Special memory locations
C. Temporary registers
D. TLB
Select an option to see the answer and solution.
When dealing with multiple devices interrupts, which mechanism is easy to implement?
A. Polling method
B. Vectored interrupts
C. Interrupt nesting
D. None of the mentioned
Select an option to see the answer and solution.
The larger memory placed between the primary cache and the memory is called . . . . . . . .
A. Level 1 cache
B. Level 2 cache
C. EEPROM
D. TLB
Select an option to see the answer and solution.
The duration between the read and the mfc signal is . . . . . . . .
A. Access time
B. Latency
C. Delay
D. Cycle time
Select an option to see the answer and solution.
In set-associative technique, the blocks are grouped into . . . . . . . . sets.
Select an option to see the answer and solution.
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
A. ISA
B. ANSA
C. Super-scalar
D. All of the mentioned
Select an option to see the answer and solution.
When parameters are being passed on to the subroutines they are stored in . . . . . . . .
A. Registers
B. Memory locations
C. Processor stacks
D. All of the mentioned
Select an option to see the answer and solution.
The disadvantage of the EPROM chip is . . . . . . . .
A. The high cost factor
B. The low efficiency
C. The low speed of operation
D. The need to remove the chip physically to reprogram it
Select an option to see the answer and solution.
. . . . . . . . is generally used to increase the apparent size of physical memory.
A. Secondary memory
B. Virtual memory
C. Hard-disk
D. Disks
Select an option to see the answer and solution.
The IDE bus is used to connect . . . . . . . .
A. RAM and processor
B. GPU and processor
C. Both Harddisk and CD/DVD drives and Processor
D. Only CD/DVD drives and Processor
Select an option to see the answer and solution.
The minimum time delay between two successive memory read operations is . . . . . . . .
A. Cycle time
B. Latency
C. Delay
D. None of the mentioned
Select an option to see the answer and solution.
. . . . . . . . signal enables the processor to wait for the memory operation to complete.
Select an option to see the answer and solution.
The BSY signal signifies . . . . . . . .
A. The BUS is busy
B. The controller is busy
C. The Initiator is busy
D. The Target is Busy
Select an option to see the answer and solution.
For the synchronization of the read head, we make use of a . . . . . . . .
A. Framing bit
B. Synchronization bit
C. Clock
D. Dirty bit
Select an option to see the answer and solution.
The main advantage of multiple bus organisation over a single bus is . . . . . . . .
A. Reduction in the number of cycles for execution
B. Increase in size of the registers
C. Better Connectivity
D. None of the mentioned
Select an option to see the answer and solution.
The virtual memory bridges the size and speed gap between . . . . . . . . and . . . . . . . .
A. RAM and ROM
B. RAM and Secondary memory
C. Processor and RAM
D. None of the mentioned
Select an option to see the answer and solution.
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is . . . . . . . .
A. 0.0021
B. 0.0038
C. 0.0064
D. 0.0128
Select an option to see the answer and solution.