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Computer Science · all questions

Computer Architecture
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The pipelining process is also called as . . . . . . . .

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. . . . . . . . symbol is used to signify write back mode.

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. . . . . . . . signal is sent by the initiator to indicate the duration of the transaction.

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Since it uses the out of order mode of execution, the results are stored in . . . . . . . .

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When dealing with multiple devices interrupts, which mechanism is easy to implement?

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The larger memory placed between the primary cache and the memory is called . . . . . . . .

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The duration between the read and the mfc signal is . . . . . . . .

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In set-associative technique, the blocks are grouped into . . . . . . . . sets.

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For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

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When parameters are being passed on to the subroutines they are stored in . . . . . . . .

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The disadvantage of the EPROM chip is . . . . . . . .

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. . . . . . . . is generally used to increase the apparent size of physical memory.

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The IDE bus is used to connect . . . . . . . .

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The minimum time delay between two successive memory read operations is . . . . . . . .

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. . . . . . . . signal enables the processor to wait for the memory operation to complete.

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The BSY signal signifies . . . . . . . .

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For the synchronization of the read head, we make use of a . . . . . . . .

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The main advantage of multiple bus organisation over a single bus is . . . . . . . .

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The virtual memory bridges the size and speed gap between . . . . . . . . and . . . . . . . .

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Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is . . . . . . . .

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