Q182
What is the maximum clock frequency at which following circuit can be operated without timing violations? Assume that the combinational logic delay is 10 ns and the clock duty cycle varies form 40% to 60%
What is the maximum clock frequency at which following circuit can be operated without timing violations? Assume that the combinational logic delay is 10 ns and the clock duty cycle varies form 40% to 60%
A.
100 MHz
B.
50 MHz
C.
40 MHz
AnswerD.
25 MHz
Answer: Option C
Solution
Answer: Option C
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