The fan put of a 7400 NAND gate is
A. 2TTL
B. 5TTL
C. 8TTL
D. 10TTL
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The universal gate is ___________
A. NAND gate
B. OR gate
C. AND gate
D. None of the above
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An OR gate has 6 inputs. The number of input words in its truth table are
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In which of the following base systems is 123 not a valid number?
A. Base 10
B. Base 16
C. Base 8
D. Base 3
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In case of OR gate, no matter what the number of inputs, a
A. 1 at any input causes the output to be at logic 1
B. 1 at any input causes the output to be at logic 0
C. 0 any input causes the output to be at logic 0
D. 0 at any input causes the output to be at logic 1.
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The number of Boolean functions that can be generated by n variables is equal to
A. 2n
B. 22n
C. 22n - 1
D. 2n - 1
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Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits?
A. State Reduction
B. State Minimization
C. State Assignment
D. State Evaluation
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Positive logic in a logic circuit is one in which
A. logic 0 and 1 are represented by 0 and positive voltage respectively
B. logic 0 and, -1 are represented by negative and positive voltages respectively
C. logic 0 voltage level is higher than logic 1 voltage level
D. logic 0 voltage level is lower than logic 1 voltage level.
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Digital circuit can be made by the repeated use of ___________
A. OR gates
B. NOT gates
C. NAND gates
D. None of the above
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Pick out the CORRECT statement:
A. In a positional number system, each symbol represents the same value irrespective of its position
B. The highest symbol in a position number system as a value equal to the number of symbols in the system
C. It is not always possible to find the exact binary
D. Each hexadecimal digit can be represented as a sequence of three binary symbols.
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"What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA?
A. Propagation delay will increase
B. FPGA area will increase
C. Wastage of logic modules will not be prevented
D. Number of interconnected paths in device will decrease "
A. A & B
B. C & D
C. A & D
D. B & C
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A debouncing circuit is
A. An astable MV
B. A bistable MV
C. A latch
D. A monostable MV
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The inverter is ___________
A. NOT gate
B. OR gate
C. AND gate
D. None of the above
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Most of the digital computers do not have floating point hardware because
A. Floating point hardware is costly
B. It is slower than software
C. It is not possible to perform floating point addition by hardware
D. Of no specific reason
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What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view?
A. Input operation
B. Tristate output operation
C. Bi-directional I/O pin access
D. All of the above
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The binary number 10101 is equivalent to decimal number ___________.
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Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is.
A. 100 CPS
B. 120 CPS
C. 12 CPS
D. None of the above
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An AND gate will function as OR if
A. All the inputs to the gates are “1”
B. All the inputs are ‘0’
C. Either of the inputs is “1”
D. All the inputs and outputs are complemente'
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Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?
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The NOR gate is OR gate followed by ___________.
A. AND gate
B. NAND gate
C. NOT gate
D. None of the above
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