In intel's IA-32 architecture there is a separate 16 bit address space for the I/O devices.
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A . . . . . . . . is used to restore the contents of the cells.
A. Sense amplifier
B. Refresh counter
C. Restorer
D. None of the mentioned
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The unit which acts as an intermediate agent between memory and backing store to reduce process time is . . . . . . . .
A. TLB's
B. Registers
C. Page tables
D. Cache
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Memory can be accessed in ARM systems by . . . . . . . . instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
A. i, ii, iii
B. i, ii
C. i, iv, v
D. iii, iv, v
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The starting address of the page table is stored in . . . . . . . .
A. TLB
B. R0
C. Page table base register
D. None of the mentioned
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. . . . . . . . translates the logical address into a physical address.
A. MMU
B. Translator
C. Compiler
D. Linker
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When dealing with the branching code the assembler . . . . . . . .
A. Replaces the target with its address
B. Does not replace until the test condition is satisfied
C. Finds the Branch offset and replaces the Branch target with it
D. Replaces the target with the value specified by the DATAWORD directive
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The PCi BUS allows us to connect . . . . . . . . I/O devices.
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Once the BUS is granted to a device . . . . . . . .
A. It activates the BUS busy line
B. Performs the required operation
C. Raises an interrupt
D. All of the mentioned
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The instruction, Add R1,R2,R3 in RTN is . . . . . . . .
A. R3=R1+R2+R3
B. R3<-[R1]+[R2]+[R3]
C. R3=[R1]+[R2]
D. R3<-[R1]+[R2]
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The chip can be disabled or cut off from an external connection using . . . . . . . .
A. Chip select
B. LOCK
C. ACPT
D. RESET
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The division operation in IA-32 is a single operand instruction so it is assumed that . . . . . . . .
A. The divisor is stored in the EAX register
B. The dividend is stored in the EAC register
C. The divisor is stored in the accumulator
D. The dividend is stored in the accumulator
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If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.
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. . . . . . . . is used to implement virtual memory organisation.
A. Page table
B. Frame table
C. MMU
D. None of the mentioned
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The instruction used to multiply operands yielding a double integer outcome is . . . . . . . .
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The mode of transmission of data, where one bit is sent for each clock cycle is . . . . . . . .
A. Asynchronous
B. Parallel
C. Serial
D. Isochronous
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What does the hardwired control generator consist of?
A. Decoder/encoder
B. Condition codes
C. Control step counter
D. All of the mentioned
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If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
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A narrow SCSI BUS has . . . . . . . . data lines.
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The difference between DRAM's and SDRAM's is/are . . . . . . . .
A. The DRAM's will not use the master slave relationship in data transfer
B. The SDRAM's make use of clock
C. The SDRAM's are more power efficient
D. None of the mentioned
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