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Computer Science · all questions

Computer Architecture
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In intel's IA-32 architecture there is a separate 16 bit address space for the I/O devices.

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A . . . . . . . . is used to restore the contents of the cells.

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The unit which acts as an intermediate agent between memory and backing store to reduce process time is . . . . . . . .

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Memory can be accessed in ARM systems by . . . . . . . . instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical

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The starting address of the page table is stored in . . . . . . . .

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. . . . . . . . translates the logical address into a physical address.

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When dealing with the branching code the assembler . . . . . . . .

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The PCi BUS allows us to connect . . . . . . . . I/O devices.

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Once the BUS is granted to a device . . . . . . . .

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The instruction, Add R1,R2,R3 in RTN is . . . . . . . .

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The chip can be disabled or cut off from an external connection using . . . . . . . .

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The division operation in IA-32 is a single operand instruction so it is assumed that . . . . . . . .

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If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.

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. . . . . . . . is used to implement virtual memory organisation.

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The instruction used to multiply operands yielding a double integer outcome is . . . . . . . .

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The mode of transmission of data, where one bit is sent for each clock cycle is . . . . . . . .

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What does the hardwired control generator consist of?

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If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).

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A narrow SCSI BUS has . . . . . . . . data lines.

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The difference between DRAM's and SDRAM's is/are . . . . . . . .

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