The order in which the return addresses are generated and used is . . . . . . . .
A. LIFO
B. FIFO
C. Random
D. Highest priority
Select an option to see the answer and solution.
When DRAM's are used to build a complex large memory, then the controller only provides the refresh counter.
Select an option to see the answer and solution.
MFC is used to . . . . . . . .
A. Issue a read signal
B. Signal to the device that the memory read operation is complete
C. Signal the processor the memory operation is complete
D. Assign a device to perform the read operation
Select an option to see the answer and solution.
In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is . . . . . . . .
A. EA = 5+R1
B. EA = R1
C. EA = [R1]
D. EA = 5+[R1]
Select an option to see the answer and solution.
How is a privilege exception dealt with?
A. The program is halted and the system switches into supervisor mode and restarts the program execution
B. The Program is stopped and removed from the queue
C. The system switches the mode and starts the execution of a new process
D. The system switches mode and runs the debugger
Select an option to see the answer and solution.
The most efficient method followed by computers to multiply two unsigned numbers is . . . . . . . .
A. Booth algorithm
B. Bit pair recording of multipliers
C. Restoring algorithm
D. Non restoring algorithm
Select an option to see the answer and solution.
From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer.
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
A. i and ii
B. ii
C. i, ii and iv
D. iv
Select an option to see the answer and solution.
The most Flexible way of logging the return addresses of the subroutines is by using . . . . . . . .
A. Registers
B. Stacks
C. Memory locations
D. None of the mentioned
Select an option to see the answer and solution.
The register used to serve as PC is called as . . . . . . . .
A. Indirection register
B. Instruction pointer
C. R-32
D. None of the mentioned
Select an option to see the answer and solution.
Distributed arbitration makes use of . . . . . . . .
A. BUS master
B. Processor
C. Arbitrator
D. 4-bit ID
Select an option to see the answer and solution.
The time delay between two successive initiations of memory operation . . . . . . . .
A. Memory access time
B. Memory search time
C. Memory cycle time
D. Instruction delay
Select an option to see the answer and solution.
The instruction, Add #45,R1 does . . . . . . . .
A. Adds the value of 45 to the address of R1 and stores 45 in that address
B. Adds 45 to the value of R1 and stores it in R1
C. Finds the memory location 45 and adds that content to that of R1
D. None of the mentioned
Select an option to see the answer and solution.
The DMA transfers are performed by a control circuit called as . . . . . . . .
A. Device interface
B. DMA controller
C. Data controller
D. Overlooker
Select an option to see the answer and solution.
The Sun micro systems processors usually follow . . . . . . . . architecture.
A. CISC
B. ISA
C. ULTRA SPARC
D. RISC
Select an option to see the answer and solution.
The transformation between the Parallel and serial ports is done with the help of . . . . . . . .
A. Flip flops
B. Logic circuits
C. Shift registers
D. None of the mentioned
Select an option to see the answer and solution.
The higher order bits of the virtual address generated by the processor forms the . . . . . . . .
A. Table number
B. Frame number
C. List number
D. Page number
Select an option to see the answer and solution.
There exists a separate block to increment the PC in multiple BUS organisation.
Select an option to see the answer and solution.
The signal used to initiate device select . . . . . . . .
A. IRDY#
B. S/BE
C. DEVSEL#
D. IDSEL#
Select an option to see the answer and solution.
DDR SDRAM's perform faster data transfer by . . . . . . . .
A. Integrating the hardware
B. Transferring on both edges
C. Improving the clock speeds
D. Increasing the bandwidth
Select an option to see the answer and solution.
The method which offers higher speeds of I/O transfers is . . . . . . . .
A. Interrupts
B. Memory mapping
C. Program-controlled I/O
D. DMA
Select an option to see the answer and solution.