A microcontroller differs from a microprocessor in terms of
A. I/O interfaces and instruction decoding
B. Memory configuration and I/O interfaces
C. Data bus width and clock speed
D. Memory configuration and instruction decoding
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Consider the following 8085 interrupts:
1. TRAP
2. INTR
3. RST 6
4. RST 7.5
5. RST 0
The software interrupt are
A. 1 and 3 only
B. 2 and 5 only
C. 3 and 5 only
D. 1, 2, 3, 4 and 5
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Match
List-I with
List-II and select the correct answer using the options given below the lists:
List-I (Pre terminals)
List-II (Applications)
a. SID, SOD
1. Wait state
b. Ready
2. Interrupt
c. TRAP
3. Serial data transfer
d. ALE
4. Memory of I/O read/wire
5. Address latch control
A. a-3, b-1, c-5, d-2
B. a-3, b-1, c-2, d-5
C. a-4, b-3, c-2, d-5
D. a-4, b-3, c-1, d-2
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Define the type of instruction with its addressing mode. (8086 ALP) IN AX, 04H
A. Arithmetic, indexed addressing
B. Data transfer port addressing
C. Logical, based indexed addressing
D. Branching, register indirect addressing
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Consider the following 8085 instructions:
MVI A, A9H
MVI B, 57H
ADD B
ORA A
The flag status (S, Z, CY) after the instruction ORA A is executed, is
A. (0, 1, 1)
B. (0, 1, 0)
C. (1, 0, 0)
D. (1, 0, 1)
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Consider the following:
1. Sign Flag
2. Zero Flag
3. Carry Flag
4. Parity Flag
Which of the above flags of 8085 get affected by the instruction SUB B?
A. 1 and 2
B. 1 and 3
C. 3 and 4
D. 1, 2, 3 and 4
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In a microprocessor, when a CPU is interrupted, it
A. Stops execution of instructions
B. Acknowledges interrupt and branches of subroutine
C. Acknowledges interrupt and continues
D. Acknowledges interrupt and waits for the next instruction from the interrupting device
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Consider the following statements:
The SIM instruction outputs the contents of accumulator to define:
1. Interrupt mask bit.
2. Interrupt pending bit.
3. Serial input data line.
4. Serial output data line.
Which of the statements given above are correct?
A. 1 and 2
B. 2 and 3
C. 3 and 4
D. 1 and 4
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A microprocessor with 12-bit address bus will be able to access . . . . . . . . kilobytes of memory.
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Which one of the following interrupts is both level and edge sensitive?
A. RST 7.5
B. RST 5.5
C. TRAP
D. INTR
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Which one of the following is NOT a vectored interrupt?
A. TRAP
B. INTR
C. RST 3
D. RST 7.5
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Consider the following statements regarding programmable interrupt controller 8259A:
1. 8259A is specifically designed for use with the interrupt signals (INTR/INT) of 8085 microprocessor.
2. It can solve eight levels of interrupt priorities in a variety of modes.
3. With additional 8259A devices, the priority scheme can be expanded to 32 levels.
Which of the above statement is/are not correct?
A. 1 and 3
B. 2 only
C. 3 only
D. 1 and 2
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Which one of the following addressing modes is used to compute the address of the operand by adding a constant value to the content of a register?
A. Immediate addressing
B. Indexed addressing
C. Absolute addressing
D. Direct addressing
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For 8085 microprocessor, the instruction RST 6 restarts subroutine at address:
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In 8085 microprocessor system, the direct addressing instructions is
A. Mov A, B
B. Mov B, OAH
C. Mov C, M
D. STA adds
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PUSH a
PUSH b
PUSH c
POP AX
POP BX
SUB AX, BX
POP BX
ADD AX, BX
The expression computed by the above program and stored in AX is
A. a + b - c
B. c + b - a
C. c - b + a
D. c - b - a
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In IC 8085 Microprocessor TRAP interrupt ISR is at which memory address?
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The output data lines of microprocessor and memories are usually tristated, because:
A. More than one device can transmit information over the data bus by enabling only one device at a time
B. More than one device can transmit information over the data bus at the same time
C. The data lines can be multiplexed for both input and output
D. It increases the speed of data transfer over the data bus
Select an option to see the answer and solution.