‘Burst refresh’ in DRAM is also called
A. Concentrated refresh
B. Distributed refresh
C. Hidden refresh
D. None of the above
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When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode
A. None of the numbers is changed
B. .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed
C. .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed
D. Both Ihe numbers are changed and their exponents are, made equal to -5
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In 8085, the pins for SID and SOD are
A. 4 and 5 respectively
B. 5 and 4 respectively
C. 3 and 4 respectively
D. 4 and 3 respectively
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An Input/Output processor controls the flow of information between
A. Cache memory and Input/Output devices
B. Main memory and Input/Output devices
C. Two Input/Output devices
D. Cache and main memory
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Of the following circuits, the one which involves storage is
A. RS Latch
B. Mux
C. Nand
D. Decoder
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MS Access is a DBMS software.
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Which of the following is not a general purpose peripheral?
A. Input/Output port
B. Programmable interrupt controller
C. Programmable CRT controller
D. Programmable interval timer
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In Fortran 77 a variable name can contain special characters.
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It is possible to copy a file in the same directory.
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What is the addressing mode used in instruction MOV M, C?
A. Direct
B. Indirect
C. Induced
D. Immediate
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In microprocessor's stack, what does the operation push cx means?
A. Ch = [sp - 1], cl = [sp - 2] and sp = sp - 2
B. Ch = [sp], cl = [sp - 1] and sp = sp - 2
C. Ch = [sp + 1], cl = [sp] and sp = sp + 2
D. Ch = [sp], cl = [sp + 1] and sp = sp + 2
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How many bits are used as conditional flags in the flag register of 8086?
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If B7 and B6 bits of mode register in 8237 are set to 11, which mode of operation is selected?
A. Cascade mode
B. Single mode
C. Block mode
D. Demand mode
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The address bus of Intel 8085 is 16-bit wide and hence the memory which can be accessed by this address bus is
A. 2 k bytes
B. 4 k bytes
C. 16 k bytes
D. 64 k bytes
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What is the size(in bits) of the stack pointer in 8085?
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Interrupt latency is the time elapsed between:
A. Occurrence of an interrupt and its detection by the CPU
B. Assertion of an interrupt and the start of the associated ISR
C. Assertion of an interrupt and the completion of the associated ISR
D. Start and completion of associated ISR
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1. Program Counter (PC) Pushed to Stack
2. Generate LCALL to ISR
3. Complete Execution of instruction in progress
4. Clear the interrupt flag
5. Set interrupt in progress
Correct order of execution of action taken by 8051 micro-controllers when an interrupt occurs:
A. 3, 1, 4, 5, 2
B. 1, 2, 4, 5, 3
C. 3, 4, 2, 5, 1
D. 1, 3, 2, 4, 5
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Which of the 8086 instruction can be used to fetch a string of 16-bit word stored in memory, automatically incrementing the memory pointer?
A. LODW with the direction flag reset
B. LODSW with the direction flag reset
C. LODS with the direction flag reset
D. LOW with the direction flag reset
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Which of the following are two most commonly used industry standards for interchip serial communications?
A. PCI & SPI
B. RS-232 & RS-242
C. I2C & SPI
D. IS-231 & S-212
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Consider the following instruction of 8085 µP.
1. MOV M, A
2. ADD C
3. MVI A, FF
4. CMP M
Which of these cause change in the status of flag(s)?
A. 1 and 2
B. 1, 2 and 3
C. 3 and 4
D. 2 and 4
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