The method used to transfer data from I/O units to memory by suspending the memory-CPU data transfer for one memory cycle is called
A. I/O spooling
B. Cycle stealing
C. Line conditioning
D. Demand paging
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Description of LAHF instruction in 8086 processor
A. Store A register to segment register
B. Load A register to segment register
C. Store A register from flags
D. Load A register from flags
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The RST 5.5 interrupt service routine starts from location
A. 0020 H
B. 0024 H
C. 0028 H
D. 002C H
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Consider the following statements regarding 8051 microcontroller:
1. The size of RAM in 8051 is 128 bytes.
2. RAM locations 00-1FH are assigned to the register banks and stack.
3. RAM location 20-2FH are available as a place to save byte-sized data.
Which of the above statements are correct?
A. 1 and 2 only
B. 1 and 3 only
C. 2 and 3 only
D. 1, 2 and 3
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The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085 processor executes the instruction LDA 2003 H is
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What is the activity of the microprocessor 8086/8085 when the signals S S 0 , DT/ R and IO/ M are 1, 0 and 1 respectively in minimum mode?
A. Read memory
B. Read I/O port
C. Code Access
D. Write I/O port
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A reserved area in RAM used for temporary storage of data, return addresses and content of registers during subroutine calls and interrupts is called:
A. Accumulator
B. Flags
C. Index register
D. Stack
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The 8085 microprocessor instructions with required number of T states are given below. Which pair is correctly matched?
A. STAX ⟺ 8 T-states
B. SPHL ⟺ 6 T-states
C. SIM ⟺ 7 T-states
D. STA ⟺ 12 T-states
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Match
List-I correctly with
List-II and select your answer using the options given below:
List-I (Request)
List-II (Device)
a. Interrupt
1. I/O device
b. Wait
2. DMA controller
c. Hold
3. Memory
A. a-1, b-2, c-3
B. a-1, b-3, c-2
C. a-2, b-1, c-3
D. a-2, b-3, c-1
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The frequency of the driving network connected between pins 1 and 2 of a 8086 chip must be
A. Equal to the desired clock frequency
B. Twice the desired clock frequency
C. Four times the desired clock frequency
D. Eight times the desired clock frequency
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In an 8085 microprocessor system, the RST instruction will cause an interrupt
A. Only if an interrupt service routine is not being executed
B. Only if a bit in the interrupt mask is made 0
C. Only if interrupts have been enabled by an EI instruction
D. None of the above
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How many hardware interrupts are there in 8086?
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The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP?
A. It is level triggered
B. It is negative edge triggered
C. It is positive edge triggered
D. It is both positive edge triggered and level triggered
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The type of device used to interface a parallel data format with external equipment's serial format is
A. Key matrix
B. UART
C. Memory chip
D. Serial-in, parallel-out
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Which of the following interrupts has the lowest priority?
A. RST 5.5
B. RST 7.6
C. TRAP
D. INTR
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After assembly in 8086, any errors in program syntax can be found by examining the . . . . . . . . file.
A. List
B. Source
C. Main
D. Object
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How may interrupt request lines are available in programmable interrupt controller 8259A?
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Single-bit indicators that may be set or clear to show the results of logical or arithmetic operations are the-
A. Data pointer
B. Flags
C. Accumulator
D. Stack pointer
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In an 8086 microprocessor, the code segment (CS) register contains 2500H and index pointer (IP) contains 1000H. What will be the address of the physical memory location?
A. 25000H
B. 25500H
C. 27000H
D. 26000H
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Which of the following addressing mode is not usable in XCH instruction of 8051 microcontroller?
A. Direct Addressing
B. Indirect Addressing
C. Register Addressing
D. Immediate Addressing
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