The advantage of cycle stealing in DMA is that
1. It increases the maximum I/O transfer rate.
2. It reduces the interference by the DMA controller in the CPU's memory access.
3. It is beneficially employed for I/O device with shorter bursts of data transfer.
Which of the above statements are correct?
A. 1 and 2 only
B. 1 and 3 only
C. 2 and 3 only
D. 1, 2 and 3
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The assembler directive in 8086 called EQU
A. in forms the assembler which logical segment contains data
B. is used to assign names to variables
C. is used to assign names to constants
D. is used to explicitly assign a name an address
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During direct memory access (DMA), the INTR and INTA (interrupt and interrupt acknowledge) lines:
A. are never used
B. are used by the DMA controller to acquire the data and address bus from the microprocessor
C. are used by the I/O device to invoke an error routine if a problem occurs during DMA transfer
D. are used by the DMA controller to signal the microprocessor about the end of the current data transfer
Select an option to see the answer and solution.
In 8085 which of following has highest priority?
A. INTR
B. RST 7.5
C. RST 6.5
D. RST 5.5
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Which of the following computation will take minimum number of clock cycles, if it is implemented on 8051 micro-controller? Following is variable declaration in c code:
Unsigned int a, b;
A. b = a*a
B. b = a*3
C. b = a/3
D. b = a/4
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When the 8051 is reset and the line is HIGH, the program counter points to the first program instruction in the
A. internal code memory
B. external code memory
C. internal data memory
D. external data memory
Select an option to see the answer and solution.
On receiving an interrupt from an I/O device, the CPU
A. Halts for a predetermined time
B. Branches off to the interrupt service routine after completion of the current instruction
C. Branches off to the interrupt service routine immediately
D. Hands over control of address bus and data bus to the interrupting device
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In 8086 instruction set, the instructions to adjust the product to unpacked BCD digits during multiplication/division are
A. IMUL, MUL
B. IDIV, DIV
C. AAM, AAD
D. SHL, SAL
Select an option to see the answer and solution.
For accurate clock period in 8085 it is preferable to use
A. Crystal
B. Crystal of LC resonant circuit
C. Crystal of RC circuit
D. LC or RC circuit
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If CS = A 15 A 14 A 13 is used as the chip select logic of a 4K RAM in an 8085 system, then its memory range will be
A. 3000 H - 3FFF H
B. 7000 H - 7FFF H
C. 5000 H - 5 FFFH and 6000 H - 6 FFF H
D. 6000 H - 6 FFF H and 7000H - 7FFF H
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What is the content of accumulator (8085) after execution of the following program
MVI A, FF H
ADI 01 H
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The content of which of the following determines the state of the CPU at the end of the execute cycle (when the interrupt is recognized)?
1. Program counter
2. Processor register
3. Certain status conditions
Select the correct answer using the options given below:
A. 1 and 2
B. 2 and 3
C. 1 and 3
D. 1, 2 and 3
Select an option to see the answer and solution.
In an 8085 microprocessor using three byte instruction, the lower order address byte is placed in the memory first followed by the
higher order address byte. This is because of the design of
A. Instruction decoder and address bus
B. Instruction decoder and microprogram
C. Microprogram and address bus
D. Address bus and ALU
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A 32 KB RAM is interfaced to 8085 microprocessor starting from 20FFH. The ending address would be
A. 40 FEH
B. 40 FFH
C. A0FEH
D. A0FFH
Select an option to see the answer and solution.
MOV AL, OFAH is an example of
A. Immediate Addressing Mode
B. Direct Addressing Mode
C. Register Indirect Addressing Mode
D. Register Addressing Mode
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In 8086, if the content of the code segment register is 1 FAB and the content of the IP register is 10A1, then the effective memory address is
A. 20B51
B. 304C
C. FBC0
D. FDB5
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Which instruction in an 8085 processor can set a flag?
A. MOV B, C
B. JNZ 21 00 H
C. STA 20 00 H
D. ADD B
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Microprocessor 8085 is the enhanced version of the following with essentially the same construction set
A. 6800
B. 68000
C. 8080
D. 8000
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Consider the following instructions of 8085 microprocessor
1. MOV B, C
2. STA address
3. ORI byte
The correct sequence in the decreasing order of their respective memory space requirement is
A. 3, 2 and 1
B. 1, 3 and 2
C. 1, 2 and 3
D. 2, 3 and 1
Select an option to see the answer and solution.
In 8053/8054 timer, how many independent counters are available?
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