Q221
Open questionA 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. What is the maximum rate of addition per second when four 1-bit full adders are cascaded?
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Digital Electronics
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Q222
Open questionThe addition of the two number (1A8)16 + (67B)16 will be:
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Q223
Open questionAn array multiplier is used to find the product of a 3 bit number with a 4 bit number. How many 4 bits adders are required to perform multiplication?
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Q224
Open questionThe given circuit operates as a
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Q225
Open questionThe fan out TTL logic gate is about:
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Q226
Open questionIn the given figure shows a 4 bit serial in parallel out right shift register. The initial contents as shown are 0110. After 3 clock pulses the contents will be
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Q227
Open questionThe Boolean expression simplifies to
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Q228
Open questionDecimal 43 in Hexadecimal and BCD number system is respectively
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Q229
Open questionConsider the following statements regarding the Moore and Mealy models:
1. In the Mealy circuit, the final output depends only on the present state of memory elements.
2. In the Moore circuit, output can change in between the clock edges if the external inputs change.
3. The implementation of a logic function in Mealy circuit needs more number of states than Moore circuit.
Which of the above statements are not correct?
1. In the Mealy circuit, the final output depends only on the present state of memory elements.
2. In the Moore circuit, output can change in between the clock edges if the external inputs change.
3. The implementation of a logic function in Mealy circuit needs more number of states than Moore circuit.
Which of the above statements are not correct?
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Q230
Open questionWhich circuit is having both programmable gates
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Q231
Open questionThe logic operations of two combinational circuits given in Figure-I and Figure-II are
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Q232
Open questionA 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and to as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input and address inputs A0 and A1) as shown in the figure Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be
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Q233
Open questionHow many AND, OR and EXOR gates are required for the configuration of full adder?
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Q234
Open questionA single ROM is used to design a combinational circuit described by a truth table. What is the number of address lines in the ROM?
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Q235
Open questionMatch List-I (Boolean logic function) with List-II (Inverse of function) and select the correct answer using the options given below the lists:
| List-I | List-II |
| a. | 1. |
| b. | 2. |
| c. | 3. |
| d. | 4. |
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Q236
Open questionIn Boolean Algebra, AB + AB' is equivalent to
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Q237
Open questionOne hexa-decimal digit is sometimes referred to as:
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Q238
Open questionAn OR gate may be imagined as
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Q239
Open questionThe range of signed decimal numbers that can be represented by 6-bit 1's complement number is
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Q240
Open questionThe dual form of (A + B) is:
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