Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence
00 → 01 → 11 → 10 → 00 → . . . . .
The inputs D0 and D1 respectively should be connected as
The figure below shows a multiplexer where S1 and S0 are the select lines. I0 to I3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output. F is
The inverter 74 AL S01 has the following specifications:
IOH max = -0.4 mA, IOL max = 8 mA, IIH max = 20 µA, IIL max = -0.1 mA.
The fan out based on the above will be
In the circuit shown below Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If Vcc is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, the Boolean expression for Z is
Consider the following digital circuits:
1. Multiplexers
2. Read Only Memories
3. D-latch
4. Circuit as shown
Which of these come under the class of combinational circuits?