For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
A 4-bit Johnson counter is initialized to 0101. Every time the state 1011 is reached, the counter is re-initialized to 0000 at the next clock active edge. Again when the state 0001 is reached, the counter is initialized back to 0101 at the next clock active edge. The cycle length of the counter is
Consider the following statements regarding memory:
1. Integrated circuit RAM chips are available in both static and dynamic modes.
2. The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors.
3. The static RAM is easier to use and has shorter read and write cycles.
4. RAM and ROM chips are not available in a variety of physical sizes.
Which of the above statements are correct?
The following Finite State Machine (FSM) is used to detect a particular pattern in input data stream. Whenever the pattern is matched at input, output is set to '1' or else output is cleared to '0'. For which of the following data stream, output goes to '1' twice?
A digital CMOS IC operating at 10 MHz clock frequency consumes 100 mW power; the same IC operating at 15 MHz clock frequency consumes 140 mW power. What is the static power consumption of the IC?